Hierarchial semiconductor design

ABSTRACT

Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

RELATED APPLICATIONS

This application is a Divisional of Ser. No. 10/230,937, filed Aug. 29,2002, which is a Continuation of Ser. No. 09/031,398 filed on Feb. 26,1998, now U.S. Pat. No. 6,449,757, which are incorporated herein byreference.

FIELD OF THE INVENTION

This invention relates generally to the design of semiconductors, andmore particularly to such design that is hierarchical in nature.

BACKGROUND OF THE INVENTION

Semiconductor technology pervades most electronic devices today.Computers, televisions, videocassette recorders, cameras, etc., all usesemiconductor integrated circuits to varying degrees. For example, thetypical computer includes microprocessors and dedicated controllerintegrated circuits (i.e., video controllers, audio controllers, etc.),as well as memory, such as dynamic random-access memory. The design ofsemiconductors, therefore, is a crucial consideration of the design ofalmost any electronic device.

One type of semiconductor design is the design of semiconductor teststructures. A semiconductor integrated circuit, for example, must beable to operate in a variety of different conditions (varyingtemperatures, for example), and perform within a variety of differentspecifications (i.e., speed, power consumption, etc.). Semiconductortest structures are therefore utilized to ensure that various componentsof a given semiconductor will perform according to specification indifferent conditions. Test structures are not integrated circuits soldto end consumers as part of an electronic device, but rather are usedinternally to ascertain that the end products will perform correctly.

To aid in the design of semiconductors in general, and the design ofsemiconductor test structures in particular, software such as DesignFramework II (DF2), available from Cadence Design Systems, Inc., hasbeen developed. DF2, for example, includes an editor that permits adesigner to place various components over a semiconductor substrate asnecessary. DF2 also provides for a degree of flexibility in the designof such components. Specifically, DF2 includes parameterized cells, orpcells, that allow the designer to create customized instances of apcell every time the pcell is placed on a layer. For example, atransistor can be created and have parameters assigned thereto toprovide for control of its width, length, and number of gates. Wheninstances of the transistor are placed on the layer, different valuesmay be assigned to each of these parameters. According to the parametervalues, each instance varies in size and composition.

The pcell approach of DF2, however, is a top-down semiconductor designapproach, and thus has limitations and disadvantages associated with it.A designer may, for example, first draw a transistor, and then programthat transistor to respond to parameters that will cause various partsof the design to take on those parameter values. This can be a verycomplex, tedious and error-prone process. For example, if the designerdesires contacts to fill in the available active area space whilemaintaining a certain pitch and minimum separation from the active areaedge, the equations to accomplish this for an arbitrarily sized activearea are complex within DF2. Furthermore, these equations are specificto the transistor under development. If the designer desires to designanother parameterized object—for example, a field transistor or acontact chain—he or she needs to repeat the entire process.

Therefore, there is a need for an approach to the designing ofsemiconductors that avoids the pitfalls of top-down design. The approachshould enable a semiconductor designer to avoid having to “start fromscratch” when designing a new parameterized object. Thus, the approachshould be more flexible and easier to use than prior art designapproaches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a), 1(b), and 1(c) show diagrams of a representative hierarchyof a semiconductor test structure, according to an exemplary embodimentof the invention;

FIG. 2 shows a flowchart of a method according to an exemplaryembodiment of the invention;

FIG. 3 shows a diagram of a computer in conjunction with which anexemplary embodiment of the invention may be implemented;

FIG. 4 shows a diagram of a semiconductor memory in conjunction withwhich a semiconductor test structure hierarchically designed inaccordance with an embodiment of the invention may be tested;

FIG. 5 shows a diagram of the parameters contained within a basic atomcell, according to one embodiment of the invention amenable toimplementation in conjunction with Design Framework II (DF2) softwareavailable from Cadence Systems, Inc.;

FIG. 6 shows a table of basic atom cells, according to one embodiment ofthe invention;

FIG. 7 shows a diagram of a master cell for use in accordance with oneembodiment of the invention;

FIG. 8 shows a c9_(—)2225678 higher-order cell, according to oneembodiment of the invention;

FIG. 9 shows the c9_(—)2225678 cell of FIG. 8 after it has beenconverted into a VanDerPauw resistor, according to an embodiment of theinvention;

FIG. 10 shows a table of higher-order cells, according to one embodimentof the invention; and,

FIG. 11 shows a table of devices and structures, according to oneembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of exemplary embodiments of theinvention, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificexemplary embodiments in which the invention may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical,electrical and other changes may be made without departing from thespirit or scope of the present invention. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the present invention is defined only by the appended claims.

Those of ordinary skill within the art will appreciate that the detaileddescription is presented in accordance with the example of designing asemiconductor test structure. However, the invention itself is notlimited to the design of semiconductor test structures. Rather, theinvention may be utilized in the design of any semiconductor structure,in a manner identical to that described with respect to semiconductortest structures. The example of the semiconductor test structure is onlypresented in the detailed description specifically as an exemplarystructure, to provide for clear description of the invention.

The detailed description is divided into three sections. In the firstsection, an exemplary embodiment of the invention is described. In thesecond section, a specific embodiment of the invention that may bepracticed in conjunction with Design Framework II (DF2) softwareavailable from Cadence Design Systems, Inc., is presented. Finally, inthe third section, a conclusion of the detailed description is provided.

Exemplary Embodiment of the Invention

A description of an exemplary embodiment of the invention is provided inthis section of the detailed description. The description is provided inconjunction with reference to FIGS. 1(a), 1(b), 1(c), 2, 3 and 4. FIGS.1(a)-1(c) show diagrams of a representative hierarchy of a semiconductortest structure, according to an exemplary embodiment. FIG. 2 shows aflowchart of a method according to an exemplary embodiment, while FIG. 3shows a diagram of a computer in conjunction with which an exemplaryembodiment of the invention may be implemented. Finally, FIG. 4 shows adiagram of a semiconductor memory in conjunction with which asemiconductor test structure hierarchically designed in accordance withan embodiment of the invention may be tested.

Referring first to FIG. 1(a), a diagram of three higher-order cells,each defined by relating a number of instances of basic atom cells, isshown. Higher-order cell 100, defining type “1” higher-order cells, isdefined by relating four instances of basic atom cells, atoms 102, 104,106 and 108. Atoms 102 and 108 are instances of basic atom cells of type“1”; atom 104 is an instance of basic atom cell of type “2”; and, atom106 is an instance of basic atom cell of type “3”. The type defined byhigher order cell 100 (i.e., “1”), and the types of atoms 102, 104, 106and 108 (i.e., “1”, “2”, and “3”), are for representative purposes only,and do not specifically relate to any given type of semiconductorcomponent. Thus, the types as used in FIG. 1(a) (and as will be used inFIG. 1(b) and FIG. 1(c) as well) are for notational and descriptivepurposes only.

Furthermore, each of higher order cell 100, and atoms 102, 104, 106 and108 have a set of parameters related to its type. For example, theparameters may be related to placement, size, etc. (i.e., differentattributes of the given cell). Desirably, higher order cell 100 hasparameters that when changed also change the parameters of atoms 102,104, 106 and 108 as necessary. Thus, higher order cell 100 relates atoms102, 104, 106 and 108 to one another. Changing a parameter in cell 100that causes that cell to become larger, for example, causescorresponding changes in atoms 102, 104, 106 and 108 that make up thatinstance of cell 100.

Still referring to FIG. 1(a), two other higher-order cells are defined,cells 110 and 112. Cell 110 is made up of atoms 114, 116 and 118. Atoms114 and 116 are of type “2”, and atom 118 is of type “3”; cell 110itself defines type “2” for higher-order cells. Similarly, cell 112 ismade up of atoms 120, 122, 124, 126 and 128, where atoms 120 and 122 areof type “2”, atom 124 is of type “3”, and atoms 126, 128 and 130 are oftype “3”. Cell 112 itself defines type “3” for high-order cells. As withcell 100 and its constituent atoms, cells 110 and 112 and theirconstituent atoms each has a set of parameters related to its type.Desirably, when a parameter of either cell 110 or 112 changes, one ormore parameters of one or more of the associated constituent atoms alsochange.

The basic hierarchical structure shown in FIG. 1(a) is a powerful toolfor the design of semiconductor test structures. For example, oncehigher-order cells 100, 110 and 112 have been defined as is shown inFIG. 1(a), they may be utilized to create more complex devices andstructures, without forcing the designer to concern him or herself overdetails regarding the individual constituent atoms of the higher-ordercells. For example, the designer may wish to design a transistor. Atoms102 and 104 may be the two basic atoms necessary in such a design; eachexists independently and has significant programming therein. Cell 100,then, may be a higher-level structure, where parameters from atoms 102and 104 are inherited up to cell 100. A cell called tran, fortransistor, is then created by placing an instance of cell 100 andsetting the parameters of cell 100 such that a transistor is formed—thecell tran can then be used by anyone by setting its parameters.Transistors of different sizes and shapes can be created.

An additional level of the hierarchical structure initially described inFIG. 1(a) is shown in FIG. 1(b), which is a diagram of two devices, eachdefined by relating a number of instances of the higher-order cells thathave been defined in FIG. 1(a). Device 132, defining type “1” devices,is defined by relating three instances of higher-order cells, cells 134,136 and 138. Cells 134 and 138 are instances of cells of type “1,” ashas been defined as cell 100 of FIG. 1(a); cell 136 is an instance ofcells of type “3,” as has been defined as cell 112 of FIG. 1(a). As withFIG. 1(a), the type defined by device 132 is for representative purposesonly, and does not specifically relate to any given type ofsemiconductor component.

Each of device 132 and cells 134, 136 and 138 has a set of parametersrelated to its type. Desirably, device 132 has parameters that whenchanged also change the parameters of cells 134, 136 and 138, which inturn change the parameters of the atoms making up these cells (not shownin FIG. 1(b)). That is, changing a parameter for device 132 may change aparameter for cell 136, which as a type “3” higher-order cell has sixconstituent atoms, as has been shown in and described in conjunctionwith FIG. 1(a). Thus, the changing of the parameter for cell 136instigated by changing a parameter for device 132 also may change one ormore parameters of one or more of these six constituent atoms.

Still referring to FIG. 1(b), one other device is defined, device 140.Device 140 is made up of two instances of higher-order cells, cells 142and 144. Cell 142 is of type “2,” as has been defined as cell 110 ofFIG. 1(a), and cell 144 is of type “3,” as has been defined as cell 112of FIG. 1(a). Device 140 itself defines type “2” for devices. As withdevice 132 and its constituent higher-order cells, device 140 and itsconstituent higher-order cells each has a set of parameters related toits type. Desirably, when a parameter of device 140 changes, one or moreparameters of one or more of its constituent cells changes as well,propagating a change of one or more parameters of one or more of theatoms making up these constituent cells.

Therefore, the basic hierarchical structure shown in FIG. 1(a) isexpanded by the structure shown in FIG. 1(b). In FIG. 1(b), two devicesare defined. A designer of a semiconductor test structure may thereforeutilize these devices within the test structure, such that the designerdoes not need to concern him or herself with the actual cells making upthese devices, or the constituent atoms making up the higher-cells. Thedevices may thus be viewed as a higher abstraction than the higher-ordercells, just as the higher-order cells are a higher abstraction than thebasic atom cells. Changing the parameter of a device, for instance, maycause many changes in the parameters of the basic atom cells. Withoutthe invention, there would be no lower cells at all; all the programmingwould be done at the highest level. By comparison, under the invention,the designer only needs to change the parameter of a device, and if thedevice and its higher-order cells are defined correctly, appropriatechanges are propagated through to and made within the basic atom cells.

The hierarchical structure shown in FIG. 1(a) and extended in FIG. 1(b)may be additionally extended as shown in FIG. 1(c), which is a diagramof a semiconductor test structure, defined by relating three instancesof the devices that have been defined in FIG. 1(b). Semiconductor teststructure 146 is defined by relating two instances of devices of type“1,” devices 148 and 152, as devices of type “1” have been defined asdevice 132 of FIG. 1(b), and one instance of devices of type “2,” device150, as devices of type “2” have been defined as device 140 of FIG.1(b). The semiconductor test structure of FIG. 1(c) is forrepresentative purposes only, and does not specifically relate to anygiven type of semiconductor structure.

Each of structure 146 and devices 148, 150 and 152 has a set ofparameters related to its type. Desirably, structure 146 has parametersthat when changed also change the parameters of devices 148, 150 and152, which in turn change the parameters of the higher-order cellsmaking up these devices (not shown in FIG. 1(c)), which in turn changethe parameters of the atoms making up these cells (also not shown inFIG. 1(c)). That is, changing a parameter for structure 146 may change aparameter for device 150, which as a type “2” device has two constituenthigher-order cells, as has been shown in and described in conjunctionwith FIG. 1(b). Further, this change in a parameter for device 150 maycause a change in one of the parameters of one of the two constituenthigher-order cells, which may then cause a change in one of theparameters of one of the basic atom cells of this higher-order cell.

Thus, the semiconductor test structure of FIG. 1(c) (as based on thestructures of FIGS. 1(a) and 1(b)) may be viewed as being represented bya hierarchical data structure having four layers of abstraction: ahighest layer of abstraction, the test structure itself; a secondhighest layer of abstraction, the devices making up the test structure;a third highest layer of abstraction, the higher-order cells making upthe devices; and a lowest level of abstraction, the basic atom cellsmaking up the higher-order cells. Changing the parameters of any onelayer of abstraction causes the changing of the parameters of animmediately lower layer of abstraction, which then propagates changesdown to the lowest level of abstraction. The FIGS. 1(a), 1(b) and 1(c)may also be viewed as a computerized system, such that changing oneaspect (parameter) of the system during the design of a test structurecauses lower aspects of the system to automatically change. Note thatother layers of abstraction can be formed on top of the four shown inand described in conjunction with FIGS. 1(a), 1(b), and 1(c), such ascircuits and integrated circuit chips.

The hierarchical design of semiconductor test structures as has beenshown in and described in conjunction with FIGS. 1(a), 1(b) and 1(c)provides for advantages not found in the prior art. By abstracting eachlayer within a semiconductor test structure, for example, differentusers can be responsible for different parts of the design, withouthaving to be skilled in all aspects of the structure's design. Forinstance, one designer may be responsible for designing a library ofbasic atom cells, or a single very flexible basic atom cells. Anotherdesigner may be responsible for designing a library of higher-ordercells based on the basic atom cell or cells. Still another designer maybe responsible for designing devices based on the higher-order cells. Adesigner who is responsible for designing the structure itself can piecetogether a structure based on the devices and higher-order cells thathave already been created. Finally, an end user may use this structureto create different instances thereof by simply changing the parametersof the structure in accordance with current specifications. This isadvantageous, because this user does not have to be skilled inmanipulation of the basic atom cells, since changing the parametersthereof will be accomplished automatically by changing parameters of thestructure itself. Another advantage of the invention is that the celldesigner can build in optimal design characteristics into the cellstructure, and be guaranteed that those characteristics are retained ina specific instance of the cell placement by a cell user who may not befully aware of the optimal design characteristics. In this way, thecells can incorporate and pass on a high level of design experience andavoid the possibility of design errors caused by inexperienceddesigners.

A hierarchical semiconductor test structure design according to anexemplary embodiment of the invention has been shown and described.Those of ordinary skill within the art will appreciate that theinvention is not limited to the specific embodiment shown in anddescribed in conjunction with FIGS. 1(a)-1(c), however. For instance,there may be many more higher-order cells than the three defined in FIG.1(a), each of which may have many more constituent basic atom cells thanthe number shown in FIG. 1(a). For further instance, there may be manymore devices than the two defined in FIG. 1(b), each of which also mayhave many more constituent higher-order cells than the number shown inFIG. 1(b). Finally, the structure shown in FIG. 1(c) may have many moreconstituent devices than the number shown in FIG. 1(c).

Referring next to FIG. 2, a flowchart of a method according to anexemplary embodiment of the invention is shown. The method may beimplemented as a computerized method executed as a computer program on asuitably equipped computer (in particular, executed by a processor ofthe computer from a computer-readable medium of the computer, such as amemory). Such a computer program may be stored on a computer-readablemedium, such as a floppy disk, a compact-disc read-only-memory (CD-ROM),or a memory such as a random-access memory (RAM) or a read-only memory(ROM). The invention is not so limited. The method may be also beutilized to create a semiconductor test structure in accordance with anembodiment of the invention.

In step 200, a basic atom cell is created. This basic cell may be suchas those described in conjunction with FIG. 1(a). The basic atom cellhas at least one parameter that affects attributes thereof. The basicatom cell is the lowest abstraction within the hierarchical datastructure for the semiconductor test structure.

In step 202, higher-order cells, such as those of FIG. 1(a), arecreated. Each higher-order cell relates a plurality of instances of thebasic atom cell. Desirably, higher-order cells also have parameters thataffect attributes thereof. These parameters are such that when one ofthe parameters changes, one or more of the parameters of one or more ofthe plurality of instances of the basic atom cell related by thehigher-order cell also change. In this way, the higher-order cells are ahigher abstraction than the basic atom cell, and enable a designer towork with higher-order cells without having to specifically work withbasic atom cells.

In step 204, devices, such as those of FIG. 1(b), are created. Eachdevice relates a plurality of instances of higher-order cells.Desirably, devices also have parameters that affect attributes thereof.These parameters are also such that when one of the parameters changes,one or more of the parameters of the one or more of the plurality ofinstances of the higher-order cells also change (and thus instigatingchange to basic atom cells as well). The devices are a higherabstraction than the higher-order cells, permitting a designer to workwith devices without having to specifically work with higher-order cellsor basic atom cells.

Finally, in step 206, a test structure, such as that of FIG. 1(c), iscreated. A test structure relates a plurality of instances of devices.Desirably, test structures also have parameters that affect attributesthereof. These parameters are such that when one of them changes, one ormore of the parameters of the one or more of the plurality of instancesof the devices also change (and thus instigating change to higher-ordercells and basic atom cells as well). The structures are the highestabstraction, and permit a designer to work with a test structure withouthaving to specifically work with devices, higher-order cells, or basicatom cells.

The method of FIG. 2 thus provides for the design of a semiconductortest structure in a hierarchical manner. Each of the basic cells of step200 may be used in a number of different higher-order cells, which maybe used in a number of different devices, which may be used in a numberof different test structures. The hierarchical approach permitsspecialization as well: a designer may specifically only be skilled atcreating one of the levels of abstraction, saving his or her work in alibrary such that the designer constructing the next layer ofabstraction is able to utilize the immediately lower layer withouthaving particular skill in construction of such lower layers.

Referring next to FIG. 3, a diagram of a computer in conjunction withwhich an exemplary embodiment of the invention may be implemented isshown. Those of ordinary skill within the art will recognize that theinvention is not limited to the computer shown in FIG. 3, however. Inone embodiment, the computer is running Design Framework II (DF2)software, available from Cadence Design Systems, Inc., and inconjunction with which an embodiment of the invention may beimplemented.

Computer 310 of FIG. 3 is operatively coupled to monitor 312, pointingdevice 314, and keyboard 316. Computer 310 includes a processor (such asan Intel Pentium processor or a reduced instruction set (RISC)processor), random-access memory (RAM), read-only memory (ROM), and oneor more storage devices, such as a hard disk drive, a floppy disk drive(into which a floppy disk can be inserted), an optical disk drive, and atape cartridge drive. The memory, hard drives, floppy disks, etc., aretypes of computer-readable media. The invention is not particularlylimited to any type of computer 310. Computer 310 desirably is acomputer running a version of the UNIX operating system. Theconstruction and operation of such computers are well known within theart.

Furthermore, computer 310 may be communicatively connected to alocal-area network (LAN), a wide-area network (WAN), an Intranet, or theInternet, any particular manner by which the invention is not limitedto, and which is not shown in FIG. 3. Such connectivity is well knownwithin the art. In one embodiment, the computer includes a modem andcorresponding communication drivers to connect to the Internet via whatis known in the art as a “dial-up connection.” In another embodiment,the computer includes an Ethernet or similar hardware card to connect toa local-area network (LAN) or wide-area network (WAN) that itself isconnected to an Intranet or the Internet via what is know in the art asa “direct connection” (e.g., T1 line, etc.).

Monitor 312 permits the display of information, including computer,video and other information, for viewing by a user of the computer. Theinvention is not limited to any particular monitor 312, and monitor 312is one type of display device that may be used by the invention. Suchmonitors include cathode ray tube (CRT) displays, as well as flat paneldisplays such as liquid crystal displays (LCD's). Pointing device 314permits the control of the screen pointer provided by the graphical userinterface of operating systems. The invention is not limited to anyparticular pointing device 314. Such pointing devices include mouses,touch pads, trackballs, remote controls and point sticks. Finally,keyboard 316 permits entry of textual information into computer 310, asknown within the art, and the invention is not limited to any particulartype of keyboard.

Referring finally to FIG. 4, a diagram of a semiconductor memory inconjunction with which a semiconductor test structure hierarchicallydesigned in accordance with an embodiment of the invention may be testedis shown. That is, FIG. 4 shows a semiconductor memory for whichsemiconductor test structures designed in accordance with thehierarchical manner of an embodiment of the invention may beutilized—the reason why semiconductor test structures are necessary isto ensure that semiconductor circuits such as the memory of FIG. 4correctly perform according to specification. However, as described inthe beginning of this detailed description, the invention itself is notlimited to the design of a semiconductor test structure; the inventionmay be used in conjunction with the design of any semiconductorstructure. The design of a semiconductor test structure is merely anexemplary use, and is used specifically in the detailed description onlyas such.

FIG. 4 is specifically a schematic/block diagram illustrating generallyan architecture of one embodiment of a memory 400 in conjunction withwhich the present invention may be utilized. In the embodiment of FIG.4, memory 400 is a dynamic random access memory (DRAM). However, theinvention can be applied to other semiconductor memory devices, such asstatic random access memories (SRAMs), synchronous random accessmemories or other types of memories that include a matrix of selectivelyaddressable memory cells. Furthermore, as has been described in thebeginning of the detailed description, the invention can be applied toany type of semiconductor device, and is not limited to memory only.

Memory 400 includes a memory cell array 405, having memory cells thereinthat include floating gate transistors. X gate decoder 415 provides aplurality of gate control lines for addressing floating gate transistorsin array 405. Y source/drain decoder 420 provides a plurality ofsource/drain interconnection lines for accessing source/drain regions ofthe floating gate transistors in array 405. Input/output circuitry 425includes necessary sense amplifiers and input/output (I/O) circuitry forreading, writing, and erasing data to and from array 105. In response toaddress signals that are provided on address lines 435 during read,write, and erase operations, the operation of decoders 415 and 420 arecontrolled. The address signals are provided by a controller such as amicroprocessor that is fabricated separately or together with memory400, or otherwise provided by any other suitable circuits.

The description of an exemplary embodiment of the invention has beenprovided. Specifically, in conjunction with FIGS. 1(a)-1(c), adescription of a hierarchical manner by which semiconductor teststructures may be designed has been presented. In conjunction with FIG.2, a description of a method according to which such structures may bedesigned in accordance with the invention has been provided. Inconjunction with FIG. 3, a description of a computer in whichembodiments of the invention has been presented. Finally, in conjunctionwith FIG. 4, a description of a semiconductor memory that may be themotivation for the hierarchical design of semiconductor test structuresof the invention has also been provided.

Specific Embodiment of the Invention

A description of an exemplary embodiment of the invention has beendescribed in the previous section of the detailed description. In thissection of the detailed description, a description of a specificembodiment of the invention is presented. Specifically, the descriptionrelates to an embodiment of the invention implemented using DesignFramework II (DF2) software available from Cadence Design Systems, Inc.The description is provided in sufficient detail to enable one ofordinary skill in the art to make and use an embodiment of the inventionutilizing DF2.

Referring first to FIG. 5, a diagram of the parameters contained with abasic atom cell, according to one embodiment of the invention amenableto implementation in conjunction with DF2, is shown. Basic atom cell 500is termed a C1 cell, based upon pcell functionality available withinDF2. Pcell functionality provides for the taking of an existing geometryand parameterizing it so that when instances of that geometry areplaced, parameters can be specified that will customize that instance tomeet specific design rule requirements.

Cell 500 includes underlayer geometry 502, contacts 504 that can bearrayed into a contact block and aligned over geometry 502, metal caps506 that can be placed over each individual contact 504, and metal pad508 that can globally cover all contacts 504. Full programming controlis provided for every possible relationship of the four layers (i.e.,geometry 502, contacts 504, caps 506 and pad 508) with respect to oneanother. Cell 510 includes grid parameter 510 to ensure that allgeometries and shifts within cell 500 are accomplished in units of agrid. This ensures that cell 500 is always consistent with an underlyinggrid structure.

Geometry 502 has three associated parameters, 1x 512, 1y 514, and layer516. Lx 512 and 1y 514 are x and y values, respectively, that controlthe size of geometry 502. Layer 516 specifies the type of the base layerprovided by geometry 502 (such as nplsaa, npoly, etc., as known withinthe art). An “N” type for layer 516 turns off this base layer withincell 500.

Contacts 504 have thirteen associated parameters, cx 518, cy 520, cont522, cpx 524, cpy 526, cmx 528, cmy 530, nx 532, ny 534, ax 536, ay 538,cofx 540 and cofy 542. Cx 518 and cy 520 are x and y values,respectively, that control the size of the layer of contact 504. Cont522 specifies the type of the base layer for contacts 504. An “N” typefor cont 522 turns off this layer within cell 500. Cpx 524 and cpy 526are x and y values, respectively, that specify the pitch of the contactswithin the base layer. Cmx 528 and cmy 530 are x and y values,respectively, that specify the minimum allowed distance of the contactblock to the base layer edge provided within contacts 504.

Nx 532 and ny 534 are x and y values, respectively, that specify thenumber of contacts within the allowed area of the base layer provided bycont 522. The allowed area is the region of the base layer that isdefined by (1x minus two times cmx) and (1y minus two times cmy) indimension. A value of nx and ny of 0.0 fills up zero percent of theallowed area in the base layer with contacts (i.e., no contacts). Avalue of 1.0 for nx and ny fills 100% of the allowed area in the baselayer with contacts. A negative number for nx and ny forces the absolutevalue of that number of contacts to be placed. For example, an nx valueof negative three and an ny value of negative five creates a contactblock of three by five contacts independent of the allowed region of thebase layer.

Ax 536 and ay 538 are x and y values, respectively, that align thecontact block within the allowed region of the base layer. An ax valueof negative one pushes the contact block to the extreme left of theallowed region. An ax value of one pushes the contact block to theextreme right of the allowed region. An ax value of zero centers thecontact block within the allowed based region. Similar behavior appliesto ay 538. Fractional values between negative one and positive oneaccords proportional behavior.

While ax 536 and ay 538 produce shifts in the contact block relative tothe base layer, cofx 540 and cofy 542 are x and y values, respectively,that produce absolute shifts in addition to those produced by ax 536 and538. For example, if contacts are to be 0.1 micron off center in the xdirection and centered exactly in the y direction, the parameters are tobe set as follows: ax as zero, cofx as 0.1, ay as zero, and cofy as 0.

Thus, nx and ny calculate the size of the contact array, and ax and ayalign that array over the base layer. If nx and ny are negative, thenthe absolute value of that number is the number of contacts; forexample, if nx is minus eight and ny is minus five, then an eight byfive array of contacts is aligned over the allowable base layer. If nxand ny are positive, then it can take values from zero through one. Ifnx is one, for example, then 100% of the allowable area is filled withcontacts in the x direction. If nx is 0.5, then 50% of the allowablearea is filled within contacts in the x direction. (The allowable areais 1x minus two times cmx and 1y minus two times cmy.)

Once nx and ny have been used to determine the size of the contactarray, ax 536 and ay 538 are used to align that array over the allowablearea. If ax is one, then the contacts are pushed to the extreme right ofthe allowable area. If ax is zero, then the contacts are centered in theallowable area. If ax is minus one, then the contacts are pushed to theextreme left of the allowable area. Ay 538 behaves similarly in the ydirection.

Ax and ay shift contacts based upon a percentage of the available space.The contact offset parameters, cofx 540 and cofy 542, allow the contactsto be shifted by a fixed amount from the default positions given by ax536 and ay 538. For example, if contacts are to be shifted 0.1 micron tothe right of center, ax is set to zero and cofx is set to 0.1.

Metal caps 506 has five associated parameters, cap 544, csx 546, csy548, csofx 550, and csofy 552. Cap 544 specifies the type of the caplayer provided by metal caps 506. A value of “N” turns off the caplayer. Csx 546 and csy 548 are x and y values, respectively, thatspecify the surround of caps 506 with respect to contacts 504. Values ofzero for csofx and csofy center the caps about the contacts. Any othervalues cause offsets of the cap layer by the specified amount.

Finally, metal pad 508 has eight associated parameters, pad 554, psx556, psy 558, padrel 560, apx 562, apy 564, psofx 566 and psofy 568. Pad554 specifies the layer type of the pad layer provided by pad 508. Avalue of “N” turns off the pad layer. Psx 556 and psy 558 are x and yvalues, respectively, that control the size of the pad layer thatglobally surrounds the contact block. The effect of psy and psx dependson the setting of padrel 560.

Padrel 560 is a boolean parameter determining the effect of psx 556 andpsy 558. If padrel is set to “Y,” then the pad layer covers the contactblock by values of (csx plus psy) and (csy plus psy) in the x and ydirections, respectively (that is, the pad is placed relative to thecontact block). If padrel is set to “N,” then the size of the pad isprovided by psx and psy independent of the size of the contact block andother parameters.

Apx 562 and apy 564 are x and y values, respectively, that align the padwith respect to the contact block, and behaves in a similar fashion toax 536 and ay 536 that have already been described. Psofx 566 and psofy568 are x and y values, respectively, that offset the pads by the givenamount from the alignment that results from the values of psx, psy, apx,apy, and padrel.

As has been described, C1 cell 500 is a parameterized cell that has fourlayers: underlayer geometry (or base layer) 502, contacts layer 504,metal caps layer 506, and metal pad layer 508. The variables(parameters) within the C1 cell allow any size rectangular base layer tobe created. Contacts of any size can be put into this base layer. Capscan be placed over these contacts with any cap overlap contact dimensionin the x and y direction. The number of contacts that are placed withinthe base layer can be specified directly (e.g., nx as minus eight, ny asminus thirteen), or can be input as a percentage of the allowable areathat can hold contacts.

This allowable area is determined by subtracting two times cmx and twotimes cmy from the x and y dimensions of the base layer, respectively.For example, if 1x and 1y are 100 and 100 (specifying size of the baselayer), and cmx and cmy are 20 and 30, then the allowable area forcontacts is 60 in the x direction and 40 in the y direction. Contactsfill up this area based upon the contact size and contact pitch that isspecified. Once the number of allowable contacts are placed, then thecontacts can be shifted as a group anywhere within the allowable area.The caps over the contacts, and the metal pads, are completelyprogrammable in terms of size as well as offsets in the x and the ydirections.

The layer parameters, layer 516, cont 522, cap 544, and pad 554, areused to determine the layers that are used in cell 500. For example, thebase layer specified by layer 516 can be changed to an allowable layer.If an “N” is input in either layer, cont, cap or pad, then those layerswill not be placed. That is, if cap or cont is “N” then no contact orcap layer will be present regardless of the values any variables relatedto those layers may have.

The basic atom cell described and shown as cell 500 of FIG. 5 is termeda C1 cell. It is the most general cell, allowing full control in the xand y directions of cont, cap and pad. The contacts align to the baselayer, the caps align to the contacts, and the pad aligns to thecontacts. Other basic atom cells derived from the C1 cell are alsodesirable, to allow for easier creation of higher order-cells, andsubsequently devices and structures. FIG. 6 shows a table of such otherbasic atom cells (table 600) according to one embodiment of theinvention. Each of these other basic atom cells are derived from the C1cell, or from another cell within the table. Those of ordinary skillwithin the art can appreciate that the invention can be used to designother different types of basic cells with specialized properties andfeatures that can be used to create higher-order complex objects with aminimum of programming effort.

Referring next to FIG. 7, a diagram of a master cell for use inaccordance with one embodiment of the invention is shown. Master cell700 is completely programmable to produce any desired subcell by easilyeliminating undesired basic atom cells from master cell 700. Thus, asshown in FIG. 7, master cell 700 includes nine C1 cells, such as C1 cell702, nine 11 cells, such as 11 cell 704, and nine c1a cells, such as c1acell 706. Associated with the cells, as known to those of ordinary skillin the art of DF2 software, are a number of horizontal and verticalstretch lines, such as stretch lines 708 and 710, which adjust thepositioning of cells such as 702, 704 and 706. Using a master cellprovides for quicker generation of higher-order cells, devices andstructures because it is generally much quicker to delete elements fromthe master cell than it is to create them from a blank slate.

The parameters of the basic atom cells provide great flexibility inproducing a base layer with contacts, caps, and pad. Any orthogonalparametric structure should be able to be decomposed into an array of C1cells, for instance, with different relative orientations to oneanother. For example, a two-terminal resistor can be thought of as a C1cell on the left with layer, contacts, and pad turned on and caps off; aC1 cell in the middle with contacts, cap, and pad turned off; and a C1cell on the right with layer, contacts, pad turned on and caps turnedoff.

This two-terminal resistor can be viewed as including three C1 cellswith cell 2 oriented to cell 1 and cell 3 oriented to cell 2. This isreferred to as a c3_(—)2 structure. It may be an end test structure inand of itself, or it may be a higher-order cell structure for use inother more complex devices and structures. Another type of teststructure may be built from three C1 cells where both cell 2 and cell 3align to cell 1. This is referred to as a c3_(—)1 structure.

A VanDerPauw resistor, known within the art, can be built from ac9-2225678: cell 1 forms the body of the resistor, cells 2, 3, 4 and 5form the arms that align to cell 1, and cells 6, 7, 8, and 9 form thepads on the arms that align to cells 2, 3, 4 and 5, respectively. FIG. 8shows such a c9_(—)2225678 higher-order cell, cell 800, while FIG. 9shows such a c9_(—)2225678 cell after it has been converted into aVanDerPauw resistor, resistor 900. Higher-order cells such asc9_(—)2225678 may be referred to as elements, and can themselves bymanipulated into a vast array of parametric devices and structures.

A set of parameters referred to as shift parameters are used inhigher-order cells, devices and structures to determine the relativeorientation of the lower-level abstractions, such as C1 cells, withrespect to one another. For example, one set of shift parameters may beshift 32x, a32x, o32x (with a similar set existing for y directions).With these parameters, the alignment of cell 3 with respect to cell 2can be controlled. For example, setting shift 32x to 2, a32x to 0, ando32x to 0 centers cell 3 with respect to cell 2. Setting o32x to 0.1offsets cell 3 by 0.1 micron from the center of cell 2. The a parameterstake on values from minus one to plus one, and behave similar to the axand ay parameters that shift the contacts within the C1 cell itself,i.e., it produces a relative shift about an axis. The shift32x parameterdetermines the axis about which shifting occurs. For example, shift32xset to one shifts cell 3 about the left edge of cell 2; shift 32x set totwo shifts cell 3 about the center of cell 2, etc. The o32x parameterprovides offsets from the shift and a parameters.

Thus, a collection of higher-order cells (or elements) may be created toassist in development of even higher levels of abstractions, such asstructures and devices. The invention is not particularly limited to anyset of higher-order cells. However, a table of higher-order cellsaccording to one embodiment of the invention is shown in FIG. 10. WithinFIG. 10, table 1000 includes two columns: column 1002, which lists thehigher-order cells, and column 1004, which lists the basic atom cellsthat constitute these higher-order cells, and/or a description of thehigher-order cells.

The creation of such higher-order cells is accomplished by relatingtogether two or more basic atom cells, and attaching appropriateparameters thereto. For example, the c2 cell includes two C1 cells. EachC1 cell has its own set of parameters such as 11x, 12x, 11y, 12y, etc.In addition, there are a set of parameters that determine how the secondC1 cell is aligned to the first. That is, the combination of the set ofparameters determines how the second C1 cell is aligned to the first C1cell in the x and y directions.

Specifically, there are six parameters: shift21x, shift21y, a21x, a21y,o21x, and o21y. Shift21x determines the type of shift that layer 2 doeswith respect to layer 1 in the x direction. Shift21y determines the typeof shift that layer 2 does with respect to layer 1 in the y direction.A21x determines the percentage amount of shift in the x direction, whilea21y determines the percentage amount of shift in the y direction. O21xdetermines the absolute shift in the x direction after a21x has beenapplied, while o21y determines the absolute shift in the y directionafter a21y has been applied. The a21x and a21y parameters have possiblevalues ranging from minus one to plus one.

For further example, a c3 cell has three C1 cells that align to oneanother. Cell 2 aligns only to cell 1 but cell 3 aligns to either cell 1or to cell 2. Thus, there are two types of c3 cells: c3_(—)1 andc3_(—)2. C3_(—)1 has cell 3 aligning to cell 1 and c3_(—)2 has cell 3aligning to cell 2. The c1 and c2 cells require no extensions. The c3cell has local parameters such as 11x, 12x and 13x, and also globalparameters to determine the relative shifts of the c1, c3 and c3 cells.Thus, in c3_(—)2 there are parameters shift 32x, shift 32y, a32x, a32y,o32x, o32y, shift21x, shift21y, a21x, a21y, o21x and o21y. In c3_(—)1there are the parameters shift 31x, shift 31y, a31x, a31y, o31x, o31y,shift21x, shift21y, a21x, a21y, o21x and o21y. As a final example, a c4cell has four C1 cells that align to one another. There are fourvariations, namely c4_(—)11, c4_(—)12, c4_(—)22 and c4_(—)23.

Once a core library of higher-order cell has been created, as has beenshown in FIG. 10, a library of devices and structures can then also becreated. All devices and structures eventually lead back to basic atomcells. A table of exemplary devices and structures, and theirdescriptions, according to one embodiment of the invention is shown astable 1100 in FIG. 11. Devices are desirably built up from higher-ordercells, and structures are desirably built up from devices. Furtherlayers of abstraction are also possible, such as modules, built up fromstructures, and integrated circuit chips, built up from modules.

Thus, once structures have been created, higher levels of abstraction,such as the module, can also be created. A module has programmable pads,with structures in-between the pads. The size of the structures andtheir orientation are connected to the location, size and orientation ofthe interconnection pads. Higher level parameters may be used toconfigure the entire module, controlling all aspects of the module frompad size and pitch to inner-structure details such as transistor nibble,gate length, etc.

A description of a specific embodiment of the invention, forimplementation in conjunction with DF2 software, has been described.Those of ordinary skill within the art will appreciate that while theinvention has been described in relation to DF2 software, the inventionis not so limited. Thus, an embodiment of the invention utilizing othersoftware, or programmed from scratch, is within the scope of theinvention.

CONCLUSION

The above-mentioned shortcomings, disadvantages and problems areaddressed by various embodiments of the present invention, which will beunderstood by reading and studying the specification. One aspect of theinvention is a computerized system that includes a semiconductorstructure and a basic atom. The system also includes a hierarchy ofabstractions ordered from highest to lowest. Each abstraction relates aplurality of instances of an immediately lower abstraction; the highestabstraction corresponds to the structure, and the lowest abstractioncorresponds to the basic atom. A plurality of sets of parameters also isincluded within the system, where each set of parameters corresponds toan instance of an abstraction. Changing one of the set of parameters foran instance of an abstraction changes at least one of the set ofparameters for an instance of an immediately lower abstraction.Parameters desirably relate to attributes of an abstraction.

For example, in one embodiment, the hierarchy may have six abstractions:atoms, higher-order cells, devices, structures, and also circuits andintegrated circuit chips, ordered from lowest to highest. Each of theseabstractions has an associated set of parameters. Instances of atoms areused to create higher-order cells, instances of higher-order cells areused to create devices, and instances of devices are used to createstructures. Each instance of an abstraction relates together a pluralityof instances of an immediately lower-level abstraction. Thus, changingparameters associated with an instance of a higher-order cell, forexample, automatically changes the parameters of the instances of atomsrelated by that higher-order cell.

In this manner, once appropriate atoms and higher-order cells have beendesigned, devices and structures can be designed easily by relatingtogether instances of the atoms and higher-order cells. Mostimportantly, if the specifications governing a given structure need tobe changed, a user merely has to change the parameters for thestructure, which then affects the parameters of the instances of thelower level devices, higher-order cells, and atoms. That is, redesign ofthe structure at the atom, or even at the higher-order cell, level isnot necessary. This means that semiconductor design becomes moreintuitive, and enables modification of existing structures to create newstructures, in a non-tedious and non-time-consuming manner.

The present invention includes computerized systems, methods,hierarchical data structures, semiconductor structures,computer-readable media, basic atom cells, and computers of varyingscope. In one embodiment of the invention, the invention is implementedin conjunction with Design Framework II (DF2) software available fromCadence Design Systems, Inc. In addition to the aspects and advantagesof the present invention described in this summary, further aspects andadvantages of the invention will become apparent by reference to thedrawings and by reading the detailed description.

Hierarchical semiconductor structure design has been described. Althoughspecific embodiments have been illustrated and described herein, it willbe appreciated by those of ordinary skill in the art that anyarrangement which is calculated to achieve the same purpose may besubstituted for the specific embodiments shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the following claims and equivalents thereof.

1. A computer comprising: a processor; a first computer-readable medium; and, a computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom.
 2. The computer of claim 1, wherein the semiconductor structure design comprises a semiconductor test structure design.
 3. The computer of claim 1, wherein the program provides for a hierarchy of abstractions ordered from highest to lowest; wherein the lowest abstraction corresponding to the basic atom; and wherein the highest abstraction corresponding to the structure.
 4. The computer of claim 3, wherein each abstraction relates a plurality of instances of an immediately lower abstraction.
 5. The computer of claim 4, wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.
 6. The computer of claim 4, wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of all lower abstractions.
 7. The computer of claim 4, wherein each instance of an abstraction has a set of parameters; and wherein the set of parameters associated with an instance of an abstraction convey information related to physical characteristics of the abstraction.
 8. The computer of claim 7, wherein the information related to physical characteristics of the abstraction includes at least one of: grid placement information relating to the overall grid requirements of the semiconductor fabrication technology; physical location of the instance of the abstraction, with respect to the overall grid requirement; physical location of the instance of the abstraction, with respect to other instances of the abstraction; electrical characteristics of the instance of the abstraction; electrical characteristic limitation of required by the semiconductor fabrication technology; power consumption of the instances of the abstraction; density of the instances of the abstraction; physical size of the instances of the abstraction; connectivity information of the instance of the abstraction with respect to other instances of abstractions; and requirements specific to a particular instance of the abstraction.
 9. The computer of claim 1, wherein the semiconductor structure design comprises a semiconductor chip structure design.
 10. The computer of claim 1, wherein the computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 11. A computer comprising: a processor; a first computer-readable medium; and a computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom, wherein the program provides for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, wherein the highest abstraction corresponds to the structure, wherein each abstraction relates a plurality of instances of an immediately lower abstraction, and wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction
 12. The computer of claim 11, wherein the semiconductor structure design comprises a semiconductor test structure design.
 13. The computer of claim 11, wherein a set of parameters contains information relating to physical characteristics of the instance of an abstraction, wherein the physical characteristics are from a group consisting of: grid placement information relating to the overall grid requirements of the semiconductor fabrication technology; physical location of the instance of the abstraction, with respect to the overall grid requirement; physical location of the instance of the abstraction, with respect to other instances of the abstraction; electrical characteristics of the instance of the abstraction; electrical characteristic limitation of required by the semiconductor fabrication technology; power consumption of the instances of the abstraction; density of the instances of the abstraction; physical size of the instances of the abstraction; connectivity information of the instance of the abstraction with respect to other instances of abstractions; and requirements specific to a particular instance of the abstraction.
 14. The computer of claim 11, wherein the semiconductor structure design comprises a semiconductor chip structure design.
 15. The computer of claim 11, comprising: a second computer-readable medium; wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 16. An article comprising a computer readable medium having a computer program stored thereon for execution on a computer with instructions to utilize a basic atom cell in design of a semiconductor structure, the program article comprising: representing a hierarchical semiconductor structure design utilizing a basic atom; providing for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, wherein the highest abstraction corresponds to the semiconductor structure, wherein each abstraction relates a plurality of instances of an immediately lower abstraction, and wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.
 17. The article of claim 16, wherein the hierarchy of abstractions ordered from lowest to the highest comprises: atoms, higher order cells, devices, structures, circuits and integrated circuit chips.
 18. An article comprising a computer readable medium having a computer program stored thereon for execution on a computer with instructions to utilize a basic atom cell in design of a semiconductor structure, the program article comprising representing a hierarchical semiconductor structure design utilizing a basic atom.
 19. The article of claim 18, wherein the program article comprises: providing for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, and the highest abstraction corresponds to the semiconductor structure.
 20. The article of claim 19, wherein the program article comprises: each abstraction relates a plurality of instances of an immediately lower abstraction.
 21. The article of claim 20, wherein the program article comprises: wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.
 22. The article of claim 20, wherein the program article comprises: where any abstraction of a higher abstraction other than the atom cell is defined by instantiations of immediately lower abstractions.
 23. A computer, comprising: a first computer-readable medium; a processor; a computer program executed by the processor from the first computer-readable medium to provide for a hierarchy based semiconductor structure; wherein the hierarchical structure includes a plurality of semiconductor structure components, each with associated parameters and hierarchy levels; wherein a component with a higher hierarchy level is created by instantiating components with hierarchy levels; and wherein a modification to a parameter value of a component of a higher level of hierarchy results in automatic modification of one or more parameter values of a lower level of hierarchy.
 24. The computer of claim 23, comprising the semiconductor structure comprises a semiconductor chip structure design.
 25. The computer of claim 23, comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 26. A computer, comprising: a first computer-readable medium; a processor; and a computer program executed by the processor from the first computer-readable medium to provide for a hierarchy based semiconductor structure.
 27. The computer of claim 26, wherein the hierarchical structure includes a plurality of semiconductor structure components, each with associated parameters and hierarchy levels.
 28. The computer of claim 27, wherein a component with a higher hierarchy level is created by instantiating components with lower hierarchy levels.
 29. The computer of claim 28, wherein a modification to a parameter value of a component of a higher hierarchy level results in automatic modification of one or more parameter values of a lower hierarchy level.
 30. The computer of claim 26, wherein the semiconductor structure comprises a semiconductor chip structure design.
 31. The computer of claim 26, comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 32. A computer, comprising: a processor; a first computer-readable medium; a hierarchical structure designator computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom; and a component design computer program executed by the processor from the first computer-readable medium, capable of communicating with the hierarchical structure computer program, that permits a designer to place and modify characteristics of various electronic representations of components of a semiconductor structure.
 33. The computer of claim 32, wherein the semiconductor structure design comprises a semiconductor test structure design.
 34. The computer of claim 32, wherein the semiconductor structure design comprises a semiconductor chip structure design.
 35. The computer of claim 32, wherein the hierarchical structure computer program orders components hierarchy level from highest to lowest, wherein the lowest abstraction corresponds to the basic atom.
 36. The computer of claim 35, wherein each instance of a component relates a one or more instances of components with a lower hierarchy level.
 37. The computer of claim 36, wherein each instance of a component has a set of parameters; and wherein modification of an instance of a component of a higher hierarchy level changes at least one parameter of instances of components related by the component of a higher hierarchy level.
 38. The computer of claim 32, comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 39. A computer comprising: a processor; a first computer-readable medium; a hierarchical structure designator computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom; a component design computer program executed by the processor from the first computer-readable medium, capable of communicating with the hierarchical structure computer program, that permits a designer to place and modify characteristics of various electronic representations of components of a semiconductor structure; wherein the semiconductor structure design comprises a semiconductor test structure design; wherein the semiconductor structure design comprises a semiconductor chip structure design; wherein the hierarchical structure computer program orders components hierarchy level from highest to lowest, wherein the lowest abstraction corresponding to the basic atom; wherein each instance of a component relates a one or more instances of components with a lower hierarchy level; and wherein modification of an instance of a component of a higher hierarchy level changes at least one parameter of instances of components related by the component of a higher hierarchy.
 40. The computer of claim 39, wherein the component design computer program is Design Framework II software available from Cadence Design Systems, Inc.
 41. The computer of claim 39, comprising: data that describes the hierarchical semiconductor structure design; a second computer-readable medium; wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.
 42. A computer comprising: a processor; a computer-readable medium; and, a computer program executed by the processor from the medium to provide for designation of semiconductor design structure components by levels of hierarchy; wherein the computer program: creates one or more basic atom cells having at least one parameter that affects at least one attribute of the basic atom cell; and creates at least one cell of a higher level of hierarchy than the one or more basic atomic cells, that instantiates one or more basic atom cells; and wherein changing one or more parameters of cells of higher level of hierarchy automatically changes associated parameters of the one or more basic atom cells instantiated by the cell of higher level of hierarchy.
 43. The computer of claim 42, wherein the semiconductor structure comprises a semiconductor test structure.
 44. The computer of claim 42, wherein the semiconductor structure comprises a semiconductor chip structure.
 45. The computer of claim 42, further comprising: creating at least one device, each device relating a plurality of instances of cells; wherein changing one or more parameters of an instance of a device automatically changes associated parameters of a plurality of instances of cells related by the device.
 46. The computer of claim 45, further comprising: creating a structure, each structure relating a plurality of instances of devices, wherein changing one or more parameters of an instances of a structure automatically changes associated parameters of a plurality of instances of devices related by the structure. 